#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice.h"
#include "cydevice_trm.h"

/* UART_BUART */
#define UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
#define UART_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define UART_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
#define UART_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
#define UART_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
#define UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define UART_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define UART_BUART_sRX_RxBitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
#define UART_BUART_sRX_RxBitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
#define UART_BUART_sRX_RxBitCounter__COUNT_REG CYREG_B1_UDB07_CTL
#define UART_BUART_sRX_RxBitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
#define UART_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define UART_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define UART_BUART_sRX_RxBitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
#define UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define UART_BUART_sRX_RxBitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
#define UART_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define UART_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define UART_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define UART_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
#define UART_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
#define UART_BUART_sRX_RxBitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
#define UART_BUART_sRX_RxShifter_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define UART_BUART_sRX_RxShifter_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define UART_BUART_sRX_RxShifter_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
#define UART_BUART_sRX_RxShifter_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1
#define UART_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define UART_BUART_sRX_RxShifter_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0
#define UART_BUART_sRX_RxShifter_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1
#define UART_BUART_sRX_RxShifter_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1
#define UART_BUART_sRX_RxShifter_u0__A0_REG CYREG_B1_UDB04_A0
#define UART_BUART_sRX_RxShifter_u0__A1_REG CYREG_B1_UDB04_A1
#define UART_BUART_sRX_RxShifter_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1
#define UART_BUART_sRX_RxShifter_u0__D0_REG CYREG_B1_UDB04_D0
#define UART_BUART_sRX_RxShifter_u0__D1_REG CYREG_B1_UDB04_D1
#define UART_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define UART_BUART_sRX_RxShifter_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
#define UART_BUART_sRX_RxShifter_u0__F0_REG CYREG_B1_UDB04_F0
#define UART_BUART_sRX_RxShifter_u0__F1_REG CYREG_B1_UDB04_F1
#define UART_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define UART_BUART_sRX_RxSts__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define UART_BUART_sRX_RxSts__3__MASK 0x08u
#define UART_BUART_sRX_RxSts__3__POS 3
#define UART_BUART_sRX_RxSts__4__MASK 0x10u
#define UART_BUART_sRX_RxSts__4__POS 4
#define UART_BUART_sRX_RxSts__5__MASK 0x20u
#define UART_BUART_sRX_RxSts__5__POS 5
#define UART_BUART_sRX_RxSts__MASK 0x38u
#define UART_BUART_sRX_RxSts__MASK_REG CYREG_B1_UDB04_MSK
#define UART_BUART_sRX_RxSts__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define UART_BUART_sRX_RxSts__STATUS_REG CYREG_B1_UDB04_ST
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB04_05_A0
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB04_05_A1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB04_05_D0
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB04_05_D1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB04_05_F0
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB04_05_F1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB04_A0_A1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB04_A0
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB04_A1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB04_D0_D1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB04_D0
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB04_D1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB04_F0_F1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB04_F0
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB04_F1
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define UART_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0
#define UART_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1
#define UART_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0
#define UART_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1
#define UART_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define UART_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0
#define UART_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1
#define UART_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1
#define UART_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB07_A0
#define UART_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB07_A1
#define UART_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1
#define UART_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB07_D0
#define UART_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB07_D1
#define UART_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define UART_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1
#define UART_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB07_F0
#define UART_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB07_F1
#define UART_BUART_sTX_TxSts__0__MASK 0x01u
#define UART_BUART_sTX_TxSts__0__POS 0
#define UART_BUART_sTX_TxSts__1__MASK 0x02u
#define UART_BUART_sTX_TxSts__1__POS 1
#define UART_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define UART_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define UART_BUART_sTX_TxSts__2__MASK 0x04u
#define UART_BUART_sTX_TxSts__2__POS 2
#define UART_BUART_sTX_TxSts__3__MASK 0x08u
#define UART_BUART_sTX_TxSts__3__POS 3
#define UART_BUART_sTX_TxSts__MASK 0x0Fu
#define UART_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB07_MSK
#define UART_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define UART_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB07_ST

/* UART_RXInternalInterrupt */
#define UART_RXInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define UART_RXInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define UART_RXInternalInterrupt__INTC_MASK 0x01u
#define UART_RXInternalInterrupt__INTC_NUMBER 0u
#define UART_RXInternalInterrupt__INTC_PRIOR_NUM 1u
#define UART_RXInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0
#define UART_RXInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define UART_RXInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* UART_TXInternalInterrupt */
#define UART_TXInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define UART_TXInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define UART_TXInternalInterrupt__INTC_MASK 0x02u
#define UART_TXInternalInterrupt__INTC_NUMBER 1u
#define UART_TXInternalInterrupt__INTC_PRIOR_NUM 5u
#define UART_TXInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
#define UART_TXInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define UART_TXInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* XRES */
#define XRES__0__MASK 0x10u
#define XRES__0__PC CYREG_PRT12_PC4
#define XRES__0__PORT 12u
#define XRES__0__SHIFT 4
#define XRES__AG CYREG_PRT12_AG
#define XRES__BIE CYREG_PRT12_BIE
#define XRES__BIT_MASK CYREG_PRT12_BIT_MASK
#define XRES__BYP CYREG_PRT12_BYP
#define XRES__DM0 CYREG_PRT12_DM0
#define XRES__DM1 CYREG_PRT12_DM1
#define XRES__DM2 CYREG_PRT12_DM2
#define XRES__DR CYREG_PRT12_DR
#define XRES__INP_DIS CYREG_PRT12_INP_DIS
#define XRES__MASK 0x10u
#define XRES__PORT 12u
#define XRES__PRT CYREG_PRT12_PRT
#define XRES__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define XRES__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define XRES__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define XRES__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define XRES__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define XRES__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define XRES__PS CYREG_PRT12_PS
#define XRES__SHIFT 4
#define XRES__SIO_CFG CYREG_PRT12_SIO_CFG
#define XRES__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define XRES__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define XRES__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define XRES__SLW CYREG_PRT12_SLW

/* RxDMA */
#define RxDMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define RxDMA__DRQ_NUMBER 3u
#define RxDMA__NUMBEROF_TDS 0u
#define RxDMA__PRIORITY 0u
#define RxDMA__TERMIN_EN 0u
#define RxDMA__TERMIN_SEL 0u
#define RxDMA__TERMOUT0_EN 1u
#define RxDMA__TERMOUT0_SEL 3u
#define RxDMA__TERMOUT1_EN 0u
#define RxDMA__TERMOUT1_SEL 0u

/* USBFS_arb_int */
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_arb_int__INTC_MASK 0x400000u
#define USBFS_arb_int__INTC_NUMBER 22u
#define USBFS_arb_int__INTC_PRIOR_NUM 0u
#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_bus_reset */
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_bus_reset__INTC_MASK 0x800000u
#define USBFS_bus_reset__INTC_NUMBER 23u
#define USBFS_bus_reset__INTC_PRIOR_NUM 5u
#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_Dm */
#define USBFS_Dm__0__MASK 0x80u
#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
#define USBFS_Dm__0__PORT 15u
#define USBFS_Dm__0__SHIFT 7
#define USBFS_Dm__AG CYREG_PRT15_AG
#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
#define USBFS_Dm__BIE CYREG_PRT15_BIE
#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
#define USBFS_Dm__BYP CYREG_PRT15_BYP
#define USBFS_Dm__CTL CYREG_PRT15_CTL
#define USBFS_Dm__DM0 CYREG_PRT15_DM0
#define USBFS_Dm__DM1 CYREG_PRT15_DM1
#define USBFS_Dm__DM2 CYREG_PRT15_DM2
#define USBFS_Dm__DR CYREG_PRT15_DR
#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
#define USBFS_Dm__MASK 0x80u
#define USBFS_Dm__PORT 15u
#define USBFS_Dm__PRT CYREG_PRT15_PRT
#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define USBFS_Dm__PS CYREG_PRT15_PS
#define USBFS_Dm__SHIFT 7
#define USBFS_Dm__SLW CYREG_PRT15_SLW

/* USBFS_Dp */
#define USBFS_Dp__0__MASK 0x40u
#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
#define USBFS_Dp__0__PORT 15u
#define USBFS_Dp__0__SHIFT 6
#define USBFS_Dp__AG CYREG_PRT15_AG
#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
#define USBFS_Dp__BIE CYREG_PRT15_BIE
#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
#define USBFS_Dp__BYP CYREG_PRT15_BYP
#define USBFS_Dp__CTL CYREG_PRT15_CTL
#define USBFS_Dp__DM0 CYREG_PRT15_DM0
#define USBFS_Dp__DM1 CYREG_PRT15_DM1
#define USBFS_Dp__DM2 CYREG_PRT15_DM2
#define USBFS_Dp__DR CYREG_PRT15_DR
#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
#define USBFS_Dp__MASK 0x40u
#define USBFS_Dp__PORT 15u
#define USBFS_Dp__PRT CYREG_PRT15_PRT
#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define USBFS_Dp__PS CYREG_PRT15_PS
#define USBFS_Dp__SHIFT 6
#define USBFS_Dp__SLW CYREG_PRT15_SLW
#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15

/* USBFS_dp_int */
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_dp_int__INTC_MASK 0x1000u
#define USBFS_dp_int__INTC_NUMBER 12u
#define USBFS_dp_int__INTC_PRIOR_NUM 5u
#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep_0 */
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_0__INTC_MASK 0x1000000u
#define USBFS_ep_0__INTC_NUMBER 24u
#define USBFS_ep_0__INTC_PRIOR_NUM 4u
#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep_1 */
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_1__INTC_MASK 0x08u
#define USBFS_ep_1__INTC_NUMBER 3u
#define USBFS_ep_1__INTC_PRIOR_NUM 4u
#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_3
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep_2 */
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_2__INTC_MASK 0x10u
#define USBFS_ep_2__INTC_NUMBER 4u
#define USBFS_ep_2__INTC_PRIOR_NUM 4u
#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_4
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep_3 */
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_3__INTC_MASK 0x20u
#define USBFS_ep_3__INTC_NUMBER 5u
#define USBFS_ep_3__INTC_PRIOR_NUM 2u
#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_5
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep_5 */
#define USBFS_ep_5__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_5__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_5__INTC_MASK 0x80u
#define USBFS_ep_5__INTC_NUMBER 7u
#define USBFS_ep_5__INTC_PRIOR_NUM 4u
#define USBFS_ep_5__INTC_PRIOR_REG CYREG_NVIC_PRI_7
#define USBFS_ep_5__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_5__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep_6 */
#define USBFS_ep_6__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_6__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_6__INTC_MASK 0x100u
#define USBFS_ep_6__INTC_NUMBER 8u
#define USBFS_ep_6__INTC_PRIOR_NUM 5u
#define USBFS_ep_6__INTC_PRIOR_REG CYREG_NVIC_PRI_8
#define USBFS_ep_6__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_6__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep_7 */
#define USBFS_ep_7__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_7__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_7__INTC_MASK 0x200u
#define USBFS_ep_7__INTC_NUMBER 9u
#define USBFS_ep_7__INTC_PRIOR_NUM 6u
#define USBFS_ep_7__INTC_PRIOR_REG CYREG_NVIC_PRI_9
#define USBFS_ep_7__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_7__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep_8 */
#define USBFS_ep_8__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_8__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_8__INTC_MASK 0x400u
#define USBFS_ep_8__INTC_NUMBER 10u
#define USBFS_ep_8__INTC_PRIOR_NUM 4u
#define USBFS_ep_8__INTC_PRIOR_REG CYREG_NVIC_PRI_10
#define USBFS_ep_8__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_8__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_EP_DMA_Done_isr */
#define USBFS_EP_DMA_Done_isr__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_EP_DMA_Done_isr__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_EP_DMA_Done_isr__INTC_MASK 0x04u
#define USBFS_EP_DMA_Done_isr__INTC_NUMBER 2u
#define USBFS_EP_DMA_Done_isr__INTC_PRIOR_NUM 0u
#define USBFS_EP_DMA_Done_isr__INTC_PRIOR_REG CYREG_NVIC_PRI_2
#define USBFS_EP_DMA_Done_isr__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_EP_DMA_Done_isr__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_ep1 */
#define USBFS_ep1__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define USBFS_ep1__DRQ_NUMBER 0u
#define USBFS_ep1__NUMBEROF_TDS 0u
#define USBFS_ep1__PRIORITY 2u
#define USBFS_ep1__TERMIN_EN 1u
#define USBFS_ep1__TERMIN_SEL 0u
#define USBFS_ep1__TERMOUT0_EN 1u
#define USBFS_ep1__TERMOUT0_SEL 0u
#define USBFS_ep1__TERMOUT1_EN 0u
#define USBFS_ep1__TERMOUT1_SEL 0u

/* USBFS_EP17_DMA_Done_SR */
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__0__MASK 0x01u
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__0__POS 0
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__1__MASK 0x02u
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__1__POS 1
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__2__MASK 0x04u
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__2__POS 2
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__3__MASK 0x08u
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__3__POS 3
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__4__MASK 0x10u
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__4__POS 4
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__5__MASK 0x20u
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__5__POS 5
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__6__MASK 0x40u
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__6__POS 6
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__MASK 0x7Fu
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__STATUS_REG CYREG_B0_UDB05_ST

/* USBFS_ep2 */
#define USBFS_ep2__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define USBFS_ep2__DRQ_NUMBER 1u
#define USBFS_ep2__NUMBEROF_TDS 0u
#define USBFS_ep2__PRIORITY 2u
#define USBFS_ep2__TERMIN_EN 1u
#define USBFS_ep2__TERMIN_SEL 0u
#define USBFS_ep2__TERMOUT0_EN 1u
#define USBFS_ep2__TERMOUT0_SEL 1u
#define USBFS_ep2__TERMOUT1_EN 0u
#define USBFS_ep2__TERMOUT1_SEL 0u

/* USBFS_ep3 */
#define USBFS_ep3__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define USBFS_ep3__DRQ_NUMBER 2u
#define USBFS_ep3__NUMBEROF_TDS 0u
#define USBFS_ep3__PRIORITY 2u
#define USBFS_ep3__TERMIN_EN 1u
#define USBFS_ep3__TERMIN_SEL 0u
#define USBFS_ep3__TERMOUT0_EN 1u
#define USBFS_ep3__TERMOUT0_SEL 2u
#define USBFS_ep3__TERMOUT1_EN 0u
#define USBFS_ep3__TERMOUT1_SEL 0u

/* USBFS_ep5 */
#define USBFS_ep5__DRQ_CTL CYREG_IDMUX_DRQ_CTL1
#define USBFS_ep5__DRQ_NUMBER 4u
#define USBFS_ep5__NUMBEROF_TDS 0u
#define USBFS_ep5__PRIORITY 2u
#define USBFS_ep5__TERMIN_EN 1u
#define USBFS_ep5__TERMIN_SEL 0u
#define USBFS_ep5__TERMOUT0_EN 1u
#define USBFS_ep5__TERMOUT0_SEL 4u
#define USBFS_ep5__TERMOUT1_EN 0u
#define USBFS_ep5__TERMOUT1_SEL 0u

/* USBFS_ep6 */
#define USBFS_ep6__DRQ_CTL CYREG_IDMUX_DRQ_CTL1
#define USBFS_ep6__DRQ_NUMBER 5u
#define USBFS_ep6__NUMBEROF_TDS 0u
#define USBFS_ep6__PRIORITY 2u
#define USBFS_ep6__TERMIN_EN 1u
#define USBFS_ep6__TERMIN_SEL 0u
#define USBFS_ep6__TERMOUT0_EN 1u
#define USBFS_ep6__TERMOUT0_SEL 5u
#define USBFS_ep6__TERMOUT1_EN 0u
#define USBFS_ep6__TERMOUT1_SEL 0u

/* USBFS_ep7 */
#define USBFS_ep7__DRQ_CTL CYREG_IDMUX_DRQ_CTL1
#define USBFS_ep7__DRQ_NUMBER 6u
#define USBFS_ep7__NUMBEROF_TDS 0u
#define USBFS_ep7__PRIORITY 2u
#define USBFS_ep7__TERMIN_EN 1u
#define USBFS_ep7__TERMIN_SEL 0u
#define USBFS_ep7__TERMOUT0_EN 1u
#define USBFS_ep7__TERMOUT0_SEL 6u
#define USBFS_ep7__TERMOUT1_EN 0u
#define USBFS_ep7__TERMOUT1_SEL 0u

/* USBFS_ep8 */
#define USBFS_ep8__DRQ_CTL CYREG_IDMUX_DRQ_CTL1
#define USBFS_ep8__DRQ_NUMBER 7u
#define USBFS_ep8__NUMBEROF_TDS 0u
#define USBFS_ep8__PRIORITY 2u
#define USBFS_ep8__TERMIN_EN 1u
#define USBFS_ep8__TERMIN_SEL 0u
#define USBFS_ep8__TERMOUT0_EN 1u
#define USBFS_ep8__TERMOUT0_SEL 7u
#define USBFS_ep8__TERMOUT1_EN 0u
#define USBFS_ep8__TERMOUT1_SEL 0u

/* USBFS_EP8_DMA_Done_SR */
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__0__MASK 0x01u
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__0__POS 0
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__1__MASK 0x02u
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__1__POS 1
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__MASK 0x03u
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__MASK_REG CYREG_B0_UDB03_MSK
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__STATUS_REG CYREG_B0_UDB03_ST

/* USBFS_ord_int */
#define USBFS_ord_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ord_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ord_int__INTC_MASK 0x2000000u
#define USBFS_ord_int__INTC_NUMBER 25u
#define USBFS_ord_int__INTC_PRIOR_NUM 5u
#define USBFS_ord_int__INTC_PRIOR_REG CYREG_NVIC_PRI_25
#define USBFS_ord_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ord_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_sof_int */
#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_sof_int__INTC_MASK 0x200000u
#define USBFS_sof_int__INTC_NUMBER 21u
#define USBFS_sof_int__INTC_PRIOR_NUM 5u
#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21
#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* USBFS_USB */
#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
#define USBFS_USB__CR0 CYREG_USB_CR0
#define USBFS_USB__CR1 CYREG_USB_CR1
#define USBFS_USB__CWA CYREG_USB_CWA
#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
#define USBFS_USB__PM_ACT_MSK 0x01u
#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
#define USBFS_USB__PM_STBY_MSK 0x01u
#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
#define USBFS_USB__SOF0 CYREG_USB_SOF0
#define USBFS_USB__SOF1 CYREG_USB_SOF1
#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1

/* Clock_1 */
#define Clock_1__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define Clock_1__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define Clock_1__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define Clock_1__CFG2_SRC_SEL_MASK 0x07u
#define Clock_1__INDEX 0x00u
#define Clock_1__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define Clock_1__PM_ACT_MSK 0x01u
#define Clock_1__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define Clock_1__PM_STBY_MSK 0x01u

/* USBInDMA */
#define USBInDMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL2
#define USBInDMA__DRQ_NUMBER 8u
#define USBInDMA__NUMBEROF_TDS 0u
#define USBInDMA__PRIORITY 3u
#define USBInDMA__TERMIN_EN 0u
#define USBInDMA__TERMIN_SEL 0u
#define USBInDMA__TERMOUT0_EN 1u
#define USBInDMA__TERMOUT0_SEL 8u
#define USBInDMA__TERMOUT1_EN 0u
#define USBInDMA__TERMOUT1_SEL 0u

/* Pin_UART_Rx */
#define Pin_UART_Rx__0__MASK 0x40u
#define Pin_UART_Rx__0__PC CYREG_PRT12_PC6
#define Pin_UART_Rx__0__PORT 12u
#define Pin_UART_Rx__0__SHIFT 6
#define Pin_UART_Rx__AG CYREG_PRT12_AG
#define Pin_UART_Rx__BIE CYREG_PRT12_BIE
#define Pin_UART_Rx__BIT_MASK CYREG_PRT12_BIT_MASK
#define Pin_UART_Rx__BYP CYREG_PRT12_BYP
#define Pin_UART_Rx__DM0 CYREG_PRT12_DM0
#define Pin_UART_Rx__DM1 CYREG_PRT12_DM1
#define Pin_UART_Rx__DM2 CYREG_PRT12_DM2
#define Pin_UART_Rx__DR CYREG_PRT12_DR
#define Pin_UART_Rx__INP_DIS CYREG_PRT12_INP_DIS
#define Pin_UART_Rx__MASK 0x40u
#define Pin_UART_Rx__PORT 12u
#define Pin_UART_Rx__PRT CYREG_PRT12_PRT
#define Pin_UART_Rx__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define Pin_UART_Rx__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define Pin_UART_Rx__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define Pin_UART_Rx__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define Pin_UART_Rx__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define Pin_UART_Rx__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define Pin_UART_Rx__PS CYREG_PRT12_PS
#define Pin_UART_Rx__SHIFT 6
#define Pin_UART_Rx__SIO_CFG CYREG_PRT12_SIO_CFG
#define Pin_UART_Rx__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define Pin_UART_Rx__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define Pin_UART_Rx__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define Pin_UART_Rx__SLW CYREG_PRT12_SLW

/* Pin_UART_Tx */
#define Pin_UART_Tx__0__MASK 0x80u
#define Pin_UART_Tx__0__PC CYREG_PRT12_PC7
#define Pin_UART_Tx__0__PORT 12u
#define Pin_UART_Tx__0__SHIFT 7
#define Pin_UART_Tx__AG CYREG_PRT12_AG
#define Pin_UART_Tx__BIE CYREG_PRT12_BIE
#define Pin_UART_Tx__BIT_MASK CYREG_PRT12_BIT_MASK
#define Pin_UART_Tx__BYP CYREG_PRT12_BYP
#define Pin_UART_Tx__DM0 CYREG_PRT12_DM0
#define Pin_UART_Tx__DM1 CYREG_PRT12_DM1
#define Pin_UART_Tx__DM2 CYREG_PRT12_DM2
#define Pin_UART_Tx__DR CYREG_PRT12_DR
#define Pin_UART_Tx__INP_DIS CYREG_PRT12_INP_DIS
#define Pin_UART_Tx__MASK 0x80u
#define Pin_UART_Tx__PORT 12u
#define Pin_UART_Tx__PRT CYREG_PRT12_PRT
#define Pin_UART_Tx__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define Pin_UART_Tx__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define Pin_UART_Tx__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define Pin_UART_Tx__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define Pin_UART_Tx__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define Pin_UART_Tx__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define Pin_UART_Tx__PS CYREG_PRT12_PS
#define Pin_UART_Tx__SHIFT 7
#define Pin_UART_Tx__SIO_CFG CYREG_PRT12_SIO_CFG
#define Pin_UART_Tx__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define Pin_UART_Tx__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define Pin_UART_Tx__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define Pin_UART_Tx__SLW CYREG_PRT12_SLW

/* Pin_PowerLED */
#define Pin_PowerLED__0__MASK 0x20u
#define Pin_PowerLED__0__PC CYREG_PRT1_PC5
#define Pin_PowerLED__0__PORT 1u
#define Pin_PowerLED__0__SHIFT 5
#define Pin_PowerLED__AG CYREG_PRT1_AG
#define Pin_PowerLED__AMUX CYREG_PRT1_AMUX
#define Pin_PowerLED__BIE CYREG_PRT1_BIE
#define Pin_PowerLED__BIT_MASK CYREG_PRT1_BIT_MASK
#define Pin_PowerLED__BYP CYREG_PRT1_BYP
#define Pin_PowerLED__CTL CYREG_PRT1_CTL
#define Pin_PowerLED__DM0 CYREG_PRT1_DM0
#define Pin_PowerLED__DM1 CYREG_PRT1_DM1
#define Pin_PowerLED__DM2 CYREG_PRT1_DM2
#define Pin_PowerLED__DR CYREG_PRT1_DR
#define Pin_PowerLED__INP_DIS CYREG_PRT1_INP_DIS
#define Pin_PowerLED__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG
#define Pin_PowerLED__LCD_EN CYREG_PRT1_LCD_EN
#define Pin_PowerLED__MASK 0x20u
#define Pin_PowerLED__PORT 1u
#define Pin_PowerLED__PRT CYREG_PRT1_PRT
#define Pin_PowerLED__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL
#define Pin_PowerLED__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN
#define Pin_PowerLED__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0
#define Pin_PowerLED__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1
#define Pin_PowerLED__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0
#define Pin_PowerLED__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1
#define Pin_PowerLED__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT
#define Pin_PowerLED__PS CYREG_PRT1_PS
#define Pin_PowerLED__SHIFT 5
#define Pin_PowerLED__SLW CYREG_PRT1_SLW

/* Pin_BLE_Extra */
#define Pin_BLE_Extra__0__MASK 0x10u
#define Pin_BLE_Extra__0__PC CYREG_IO_PC_PRT15_PC4
#define Pin_BLE_Extra__0__PORT 15u
#define Pin_BLE_Extra__0__SHIFT 4
#define Pin_BLE_Extra__AG CYREG_PRT15_AG
#define Pin_BLE_Extra__AMUX CYREG_PRT15_AMUX
#define Pin_BLE_Extra__BIE CYREG_PRT15_BIE
#define Pin_BLE_Extra__BIT_MASK CYREG_PRT15_BIT_MASK
#define Pin_BLE_Extra__BYP CYREG_PRT15_BYP
#define Pin_BLE_Extra__CTL CYREG_PRT15_CTL
#define Pin_BLE_Extra__DM0 CYREG_PRT15_DM0
#define Pin_BLE_Extra__DM1 CYREG_PRT15_DM1
#define Pin_BLE_Extra__DM2 CYREG_PRT15_DM2
#define Pin_BLE_Extra__DR CYREG_PRT15_DR
#define Pin_BLE_Extra__INP_DIS CYREG_PRT15_INP_DIS
#define Pin_BLE_Extra__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define Pin_BLE_Extra__LCD_EN CYREG_PRT15_LCD_EN
#define Pin_BLE_Extra__MASK 0x10u
#define Pin_BLE_Extra__PORT 15u
#define Pin_BLE_Extra__PRT CYREG_PRT15_PRT
#define Pin_BLE_Extra__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define Pin_BLE_Extra__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define Pin_BLE_Extra__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define Pin_BLE_Extra__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define Pin_BLE_Extra__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define Pin_BLE_Extra__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define Pin_BLE_Extra__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define Pin_BLE_Extra__PS CYREG_PRT15_PS
#define Pin_BLE_Extra__SHIFT 4
#define Pin_BLE_Extra__SLW CYREG_PRT15_SLW

/* Pin_StatusLED */
#define Pin_StatusLED__0__MASK 0x02u
#define Pin_StatusLED__0__PC CYREG_PRT3_PC1
#define Pin_StatusLED__0__PORT 3u
#define Pin_StatusLED__0__SHIFT 1
#define Pin_StatusLED__AG CYREG_PRT3_AG
#define Pin_StatusLED__AMUX CYREG_PRT3_AMUX
#define Pin_StatusLED__BIE CYREG_PRT3_BIE
#define Pin_StatusLED__BIT_MASK CYREG_PRT3_BIT_MASK
#define Pin_StatusLED__BYP CYREG_PRT3_BYP
#define Pin_StatusLED__CTL CYREG_PRT3_CTL
#define Pin_StatusLED__DM0 CYREG_PRT3_DM0
#define Pin_StatusLED__DM1 CYREG_PRT3_DM1
#define Pin_StatusLED__DM2 CYREG_PRT3_DM2
#define Pin_StatusLED__DR CYREG_PRT3_DR
#define Pin_StatusLED__INP_DIS CYREG_PRT3_INP_DIS
#define Pin_StatusLED__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define Pin_StatusLED__LCD_EN CYREG_PRT3_LCD_EN
#define Pin_StatusLED__MASK 0x02u
#define Pin_StatusLED__PORT 3u
#define Pin_StatusLED__PRT CYREG_PRT3_PRT
#define Pin_StatusLED__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define Pin_StatusLED__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define Pin_StatusLED__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define Pin_StatusLED__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define Pin_StatusLED__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define Pin_StatusLED__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define Pin_StatusLED__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define Pin_StatusLED__PS CYREG_PRT3_PS
#define Pin_StatusLED__SHIFT 1
#define Pin_StatusLED__SLW CYREG_PRT3_SLW

/* isr_InDMADone */
#define isr_InDMADone__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_InDMADone__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_InDMADone__INTC_MASK 0x800u
#define isr_InDMADone__INTC_NUMBER 11u
#define isr_InDMADone__INTC_PRIOR_NUM 2u
#define isr_InDMADone__INTC_PRIOR_REG CYREG_NVIC_PRI_11
#define isr_InDMADone__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_InDMADone__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* isr_RxDMADone */
#define isr_RxDMADone__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_RxDMADone__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_RxDMADone__INTC_MASK 0x2000u
#define isr_RxDMADone__INTC_NUMBER 13u
#define isr_RxDMADone__INTC_PRIOR_NUM 3u
#define isr_RxDMADone__INTC_PRIOR_REG CYREG_NVIC_PRI_13
#define isr_RxDMADone__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_RxDMADone__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* isr_PktDecoder */
#define isr_PktDecoder__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_PktDecoder__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_PktDecoder__INTC_MASK 0x20000u
#define isr_PktDecoder__INTC_NUMBER 17u
#define isr_PktDecoder__INTC_PRIOR_NUM 7u
#define isr_PktDecoder__INTC_PRIOR_REG CYREG_NVIC_PRI_17
#define isr_PktDecoder__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_PktDecoder__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* isr_UsbSuspend */
#define isr_UsbSuspend__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_UsbSuspend__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_UsbSuspend__INTC_MASK 0x40000u
#define isr_UsbSuspend__INTC_NUMBER 18u
#define isr_UsbSuspend__INTC_PRIOR_NUM 7u
#define isr_UsbSuspend__INTC_PRIOR_REG CYREG_NVIC_PRI_18
#define isr_UsbSuspend__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_UsbSuspend__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* Clock_PktDecoder */
#define Clock_PktDecoder__CFG0 CYREG_CLKDIST_DCFG2_CFG0
#define Clock_PktDecoder__CFG1 CYREG_CLKDIST_DCFG2_CFG1
#define Clock_PktDecoder__CFG2 CYREG_CLKDIST_DCFG2_CFG2
#define Clock_PktDecoder__CFG2_SRC_SEL_MASK 0x07u
#define Clock_PktDecoder__INDEX 0x02u
#define Clock_PktDecoder__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define Clock_PktDecoder__PM_ACT_MSK 0x04u
#define Clock_PktDecoder__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define Clock_PktDecoder__PM_STBY_MSK 0x04u

/* Clock_UsbSuspend */
#define Clock_UsbSuspend__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define Clock_UsbSuspend__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define Clock_UsbSuspend__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define Clock_UsbSuspend__CFG2_SRC_SEL_MASK 0x07u
#define Clock_UsbSuspend__INDEX 0x01u
#define Clock_UsbSuspend__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define Clock_UsbSuspend__PM_ACT_MSK 0x02u
#define Clock_UsbSuspend__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define Clock_UsbSuspend__PM_STBY_MSK 0x02u

/* Pin_RemoteWakeup */
#define Pin_RemoteWakeup__0__MASK 0x20u
#define Pin_RemoteWakeup__0__PC CYREG_PRT2_PC5
#define Pin_RemoteWakeup__0__PORT 2u
#define Pin_RemoteWakeup__0__SHIFT 5
#define Pin_RemoteWakeup__AG CYREG_PRT2_AG
#define Pin_RemoteWakeup__AMUX CYREG_PRT2_AMUX
#define Pin_RemoteWakeup__BIE CYREG_PRT2_BIE
#define Pin_RemoteWakeup__BIT_MASK CYREG_PRT2_BIT_MASK
#define Pin_RemoteWakeup__BYP CYREG_PRT2_BYP
#define Pin_RemoteWakeup__CTL CYREG_PRT2_CTL
#define Pin_RemoteWakeup__DM0 CYREG_PRT2_DM0
#define Pin_RemoteWakeup__DM1 CYREG_PRT2_DM1
#define Pin_RemoteWakeup__DM2 CYREG_PRT2_DM2
#define Pin_RemoteWakeup__DR CYREG_PRT2_DR
#define Pin_RemoteWakeup__INP_DIS CYREG_PRT2_INP_DIS
#define Pin_RemoteWakeup__INTSTAT CYREG_PICU2_INTSTAT
#define Pin_RemoteWakeup__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define Pin_RemoteWakeup__LCD_EN CYREG_PRT2_LCD_EN
#define Pin_RemoteWakeup__MASK 0x20u
#define Pin_RemoteWakeup__PORT 2u
#define Pin_RemoteWakeup__PRT CYREG_PRT2_PRT
#define Pin_RemoteWakeup__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define Pin_RemoteWakeup__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define Pin_RemoteWakeup__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define Pin_RemoteWakeup__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define Pin_RemoteWakeup__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define Pin_RemoteWakeup__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define Pin_RemoteWakeup__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define Pin_RemoteWakeup__PS CYREG_PRT2_PS
#define Pin_RemoteWakeup__SHIFT 5
#define Pin_RemoteWakeup__SLW CYREG_PRT2_SLW
#define Pin_RemoteWakeup__SNAP CYREG_PICU2_SNAP

/* Timer_PktDecoder_TimerHW */
#define Timer_PktDecoder_TimerHW__CAP0 CYREG_TMR0_CAP0
#define Timer_PktDecoder_TimerHW__CAP1 CYREG_TMR0_CAP1
#define Timer_PktDecoder_TimerHW__CFG0 CYREG_TMR0_CFG0
#define Timer_PktDecoder_TimerHW__CFG1 CYREG_TMR0_CFG1
#define Timer_PktDecoder_TimerHW__CFG2 CYREG_TMR0_CFG2
#define Timer_PktDecoder_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
#define Timer_PktDecoder_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
#define Timer_PktDecoder_TimerHW__PER0 CYREG_TMR0_PER0
#define Timer_PktDecoder_TimerHW__PER1 CYREG_TMR0_PER1
#define Timer_PktDecoder_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
#define Timer_PktDecoder_TimerHW__PM_ACT_MSK 0x01u
#define Timer_PktDecoder_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
#define Timer_PktDecoder_TimerHW__PM_STBY_MSK 0x01u
#define Timer_PktDecoder_TimerHW__RT0 CYREG_TMR0_RT0
#define Timer_PktDecoder_TimerHW__RT1 CYREG_TMR0_RT1
#define Timer_PktDecoder_TimerHW__SR0 CYREG_TMR0_SR0

/* Timer_UsbSuspend_Reset */
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__0__MASK 0x01u
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__0__POS 0
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__MASK 0x01u
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define Timer_UsbSuspend_Reset_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK

/* Timer_UsbSuspend_TimerHW */
#define Timer_UsbSuspend_TimerHW__CAP0 CYREG_TMR1_CAP0
#define Timer_UsbSuspend_TimerHW__CAP1 CYREG_TMR1_CAP1
#define Timer_UsbSuspend_TimerHW__CFG0 CYREG_TMR1_CFG0
#define Timer_UsbSuspend_TimerHW__CFG1 CYREG_TMR1_CFG1
#define Timer_UsbSuspend_TimerHW__CFG2 CYREG_TMR1_CFG2
#define Timer_UsbSuspend_TimerHW__CNT_CMP0 CYREG_TMR1_CNT_CMP0
#define Timer_UsbSuspend_TimerHW__CNT_CMP1 CYREG_TMR1_CNT_CMP1
#define Timer_UsbSuspend_TimerHW__PER0 CYREG_TMR1_PER0
#define Timer_UsbSuspend_TimerHW__PER1 CYREG_TMR1_PER1
#define Timer_UsbSuspend_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
#define Timer_UsbSuspend_TimerHW__PM_ACT_MSK 0x02u
#define Timer_UsbSuspend_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
#define Timer_UsbSuspend_TimerHW__PM_STBY_MSK 0x02u
#define Timer_UsbSuspend_TimerHW__RT0 CYREG_TMR1_RT0
#define Timer_UsbSuspend_TimerHW__RT1 CYREG_TMR1_RT1
#define Timer_UsbSuspend_TimerHW__SR0 CYREG_TMR1_SR0

/* isr_RemoteWakeup */
#define isr_RemoteWakeup__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_RemoteWakeup__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_RemoteWakeup__INTC_MASK 0x40u
#define isr_RemoteWakeup__INTC_NUMBER 6u
#define isr_RemoteWakeup__INTC_PRIOR_NUM 7u
#define isr_RemoteWakeup__INTC_PRIOR_REG CYREG_NVIC_PRI_6
#define isr_RemoteWakeup__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_RemoteWakeup__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 66000000U
#define BCLK__BUS_CLK__KHZ 66000U
#define BCLK__BUS_CLK__MHZ 66U
#define CY_PROJECT_NAME "CY5672_Dongle_Bridge"
#define CY_VERSION "PSoC Creator  3.2 SP1"
#define CYDEV_CHIP_DIE_GEN4 2u
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PANTHER 13u
#define CYDEV_CHIP_DIE_PSOC4A 6u
#define CYDEV_CHIP_DIE_PSOC5LP 12u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E127069u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 6u
#define CYDEV_CHIP_MEMBER_4C 10u
#define CYDEV_CHIP_MEMBER_4D 3u
#define CYDEV_CHIP_MEMBER_4E 5u
#define CYDEV_CHIP_MEMBER_4F 7u
#define CYDEV_CHIP_MEMBER_4G 2u
#define CYDEV_CHIP_MEMBER_4H 4u
#define CYDEV_CHIP_MEMBER_4L 9u
#define CYDEV_CHIP_MEMBER_4M 8u
#define CYDEV_CHIP_MEMBER_5A 12u
#define CYDEV_CHIP_MEMBER_5B 11u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_GEN4_ES 17u
#define CYDEV_CHIP_REV_GEN4_ES2 33u
#define CYDEV_CHIP_REV_GEN4_PRODUCTION 17u
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
#define CYDEV_CONFIGURATION_ECC 1
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_ENABLE_MASK 0x20u
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_Disable
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_XRES 0
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x00002807u
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
#define CYDEV_STACK_SIZE 0x0800
#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP 
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 0
#define CYDEV_VDDA 5.0
#define CYDEV_VDDA_MV 5000
#define CYDEV_VDDD 5.0
#define CYDEV_VDDD_MV 5000
#define CYDEV_VDDIO0 5.0
#define CYDEV_VDDIO0_MV 5000
#define CYDEV_VDDIO1 5.0
#define CYDEV_VDDIO1_MV 5000
#define CYDEV_VDDIO2 5.0
#define CYDEV_VDDIO2_MV 5000
#define CYDEV_VDDIO3 5.0
#define CYDEV_VDDIO3_MV 5000
#define CYDEV_VIO0 5.0
#define CYDEV_VIO0_MV 5000
#define CYDEV_VIO1 5.0
#define CYDEV_VIO1_MV 5000
#define CYDEV_VIO2 5.0
#define CYDEV_VIO2_MV 5000
#define CYDEV_VIO3 5.0
#define CYDEV_VIO3_MV 5000
#define CYIPBLOCK_ARM_CM3_VERSION 0
#define CYIPBLOCK_P3_ANAIF_VERSION 0
#define CYIPBLOCK_P3_CAN_VERSION 0
#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
#define CYIPBLOCK_P3_COMP_VERSION 0
#define CYIPBLOCK_P3_DECIMATOR_VERSION 0
#define CYIPBLOCK_P3_DFB_VERSION 0
#define CYIPBLOCK_P3_DMA_VERSION 0
#define CYIPBLOCK_P3_DRQ_VERSION 0
#define CYIPBLOCK_P3_DSM_VERSION 0
#define CYIPBLOCK_P3_EMIF_VERSION 0
#define CYIPBLOCK_P3_I2C_VERSION 0
#define CYIPBLOCK_P3_LCD_VERSION 0
#define CYIPBLOCK_P3_LPF_VERSION 0
#define CYIPBLOCK_P3_OPAMP_VERSION 0
#define CYIPBLOCK_P3_PM_VERSION 0
#define CYIPBLOCK_P3_SCCT_VERSION 0
#define CYIPBLOCK_P3_TIMER_VERSION 0
#define CYIPBLOCK_P3_USB_VERSION 0
#define CYIPBLOCK_P3_VIDAC_VERSION 0
#define CYIPBLOCK_P3_VREF_VERSION 0
#define CYIPBLOCK_S8_GPIO_VERSION 0
#define CYIPBLOCK_S8_IRQ_VERSION 0
#define CYIPBLOCK_S8_SAR_VERSION 0
#define CYIPBLOCK_S8_SIO_VERSION 0
#define CYIPBLOCK_S8_UDB_VERSION 0
#define DMA_CHANNELS_USED__MASK0 0x000001FFu
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
